1. Technical Field
The embodiments described herein relate generally to a semiconductor memory apparatus and, more particularly, to an auto-refresh operation control circuit in a semiconductor memory apparatus.
2. Related Art
Generally, an over-driving operation is carried out to improve a sensing speed when a semiconductor memory apparatus receives an active command. If the over-driving operation is carried out, a bit line or a bit bar line is fast sensed to a target voltage. However, current consumption increases as a result of over-driving operation.
FIG. 1 is a schematic block diagram illustrating a conventional auto-refresh operation control circuit. The conventional auto-refresh control circuit includes a refresh signal generating unit 10 to receive a refresh operation signal ‘ACTR’ indicative of an refresh operation and then produce a refresh signal ‘REF’, a pulse generating unit 20 to produce a refresh operation pulse signal ‘ACTRD’, a bank active signal generating unit 30 to produce a bank active signal ‘BA’, a RAS (Row Address Strobe) time (tRAS) determining unit 40 to receive the bank active signal ‘BA’, a primary sense amplifier signal generating unit 60, a precharge signal generating unit 50 to receive an output signal ‘PCGR’ of the RAS time determining unit 40 and then produce a precharge signal ‘PCG’, an over-driving delay unit 80 to receive output signal ‘PE’ of the primary sense amplifier signal generating unit 60 and then produce a delay signal ‘OVDb’, and a secondary sense amplifier signal generating unit 70.
FIG. 2 is a circuit diagram showing the secondary sense amplifier signal generating unit 70 of FIG. 1. The secondary sense amplifier signal generating unit 70 includes a NAND gate 71 to receive a PMOS enable signal ‘PE’ from the primary sense amplifier signal generating unit 60 and the delay signal ‘OVDb’ from the over-driving delay unit 80, a first inverter 73 to invert an output signal of the NAND gate 71, a second inverter 74 to receive an output signal of the first inverter 73 and then output an over-driving operation signal ‘SAE1B’, a third inverter 75 to receive the PMOS enable signal ‘PE’, a NOR gate 72 to receive output signals of the first and third inverters 73 and 75, a fourth inverter 76 to receive an output signal of the NOR gate 72 and produce a sense amplifier latch PMOS enable signal ‘SAE2B’ for sensing an internal core voltage VCORE, and fifth to seventh inverters 77 to 79 serially coupled to each other to receive the NMOS enable signal ‘NE’ from the primary sense amplifier signal generating unit 60 and then produce a sense amplifier latch NMOS enable signal ‘SAENB’.
FIG. 3 is a timing chart showing an operation of the conventional auto-refresh operation control circuit. Referring to FIG. 3, if a refresh command is input from an external circuit, a command decoder generates the refresh operation signal ‘ACTR’ indicative of the refresh operation. The refresh operation signal ‘ACTR’ is then input into the refresh signal generating unit 10 to produce the refresh signal ‘REF’. The pulse signal ‘ACTRD’ is generated by the pulse generating unit 20, which receives the refresh signal ‘REF’. The bank active signal generating unit 30, which receives the pulse signal ‘ACTRD’, generates the bank active signal ‘BA’ having a high level. The RAS time determining unit 40 delays the bank active signal ‘BA’ and then produces the refresh precharge signal ‘PCGR’ which is input into the precharge signal generating unit 50. The precharge signal generating unit 50 produces the precharge signal ‘PCG’. The precharge signal ‘PCG’ is input to the bank active signal generating unit 30 to disable the bank active signal ‘BA’. The bank active signal ‘BA’ is also input into the primary sense amplifier signal generating unit 60 so that the PMOS enable signal ‘PE’ and the NMOS enable signal ‘NE’ are enabled. The secondary sense amplifier signal generating unit 70, to which the PMOS enable signal ‘PE’ and the NMOS enable signal ‘NE’ are applied, produces the over-driving operation signal ‘SAE1B’ for performing the over-driving operation.
Accordingly, the high-speed sensing that operates according to the over-driving operation is not needed since the read command is not input during the refresh cycle time (tREC) in the auto-refresh operation mode. However, in the conventional semiconductor memory apparatus, there is a disadvantage in that a large amount of current consumption is caused due to the over-driving operation.